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Confidential Information
Advanced information 1.00
KS8993M 3-port Integrated Switch with PHY
FEATURES
Proven 2nd generation of Integrated 3-port 10/100 Ethernet switch with 3 MACs and 2 PHYs (2+1) Non-blocking architecture to assure fast packet delivery, with 1024 MAC address table lookup and packet forwarding via store-and-forward architecture MII registers can be accessed via MDIO bus or SPI bus MII interfaces support both a MAC mode or PHY mode or 7-wire (SNI) mode Automatic MDI/MDIX crossover for 100Base-TX and 10BaseT ports with disable and enable option Support 802.1Q VLAN up to 16 group 802.1p/q tag insertion or removal on a per port basis (egress) QoS / CoS packets prioritization supports: per port, 802.1P and DiffServ based Re-mapping of 802.1p priority field and VLAN ID field per port basis LED Indicators for link, activity, full/half duplex and speed Support Port Mirroring Advanced Rate limiting Management Information Base (MIB) Power Dissipation: < 200mA including Physical transmit drivers Plastic QFP 128 Package 1.8 volt for Vcc core and 3.3 volt for I/O
Micrel-Kendin 486 Mercury Drive, Sunnyvale, CA 94085 USA (408)735-1118 http:www.Micrel.com
KS8993M Integrated 3-port 10/100 Ethernet Switch
KS8993 Block Diagram
FIFO, Flow Control, VLAN Tagging ,Priority 1K look-up Engine
Auto M DI/MD IX
10/100 T/Tx 1
10/100 M AC 2
Queue M gm nt
Auto M DI/MD IX
10/100 T/Tx 2
10/100 M AC 2
Buffer M gm nt
10/100 M AC 3
Fram e Buffers
M II or SN I C ontrol R eg I/F
SNI SPI
M IB Counters
LED1[3:1] LED2[3:1]
LED I/F
Control Registers
EEPRO M I/F
MD C & M DIO
K S 8993M
Micrel - Kendin Confidential Information
Rev. 1.00 7/12/02
KS8993M Integrated 3-port 10/100 Ethernet Switch
TABLE OF CONTENTS
KS8993 Block Diagram ...........................................................................2 1.0 Signal Description ............................................................................1
1.1 1.2 KS8993M Pin Diagram.................................................................................... 1 KS8993M Pin Description and I/O Assignment ............................................... 2
2.0 Advanced Functions ........................................................................9 2.1 Port Mirroring Support ............................................................................ 9 2.2 VLAN support ........................................................................................... 9
QoS Priority support ...................................................................................... 11 2.4 Rate Limit Support................................................................................. 12 2.5 Static MAC address table.............................................................................. 12 2.6 VLAN table .................................................................................................... 13 2.7 Dynamic MAC address table......................................................................... 14 2.8 MIB (Management Information Base) counters............................................. 14 2.3
3.0 Package Outline and Dimensions ..................................................18
LIST OF TABLES AND FIGURES
Table 1 I/O Pin Out (by pin #)............................................................................... 2
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
1.0 Signal Description 1.1 KS8993M Pin Diagram
PV31 PS0 PS1 SPIS_N SDA SCL SPIQ M DIO M DC PRSEL0 PRSEL1 DVCC DGND SCONF0 SCONF1 SCRS SCOL SMRXD0 SMRXD1 SMRXD2 SMRXD3 SMRXDV SMRXC DVCC DGND SMTXC SMTXER SMTXD0 SMTXD1 SMTXD2 SMTXD3 SMTXEN LEDSEL SMAC BPEN RST_N X2 X1 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
PV32 PV21 PV23 DGND DVCC PV12 PV13 P3_1PEN P2_1PEN P1_1PEN P3_TXQ2 P2_TXQ2 P1_TXQ2 P3_PP P2_PP P1_PP P3_TAG INS P2_TAG INS P1_TAG INS DGND DVCC P3_TAG RM P2_TAG RM P1_TAG RM TESTEN SCANEN
103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128
KENDIN
Top view
KS8993M
64 63 63 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39
AGND AVDD AGND ISET TEST2 TEST1 AGND AVDD TXM2 TXP2 AGND RXM 2 RXP2 VDDRX33 VDDTX33 TXM1 TXP1 AGND RXM 1 RXP1 NC AVDD AGND M UX2 M UX1 AGND
Micrel - Kendin Confidential Information 1
DGND DVCC NC NC NC ADVFC P2ANEN P2SPD P2DPX P2FFC NC NC NC NC DGND DVCC NC NC NC NC NC NC NC P1ANEN P1SPD P1PDX P1FFC NC NC PW RDN AGND
P1LED2 P1LED1 P1LED0 P2LED2 P2LED1 P2LED0
Rev. 1.00 7/12/02
AVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
KS8993M (3 Port 10/100 Integrated Switch with PHY)
1.2 KS8993M Pin Description and I/O Assignment
Table 1 I/O Pin Out (by pin #) Pin #
1 2 3
Pin Name
P1LED2 P1LED1 P1LED0
Type
I(pu)/O I(pu)/O I(pu)/O
Description
Port 1 LED indicators, defined as below: P1LED2 P1LED1 P1LED0 LEDSEL = 0 LINK/ACT FULLD/COL SPEED LEDSEL = 1 100LINK/ACT 10LINK/ACT FULLD
4 5 6
P2LED2 P2LED1 P2LED0
I(pu)/O I(pu)/O I(pu)/O
Note: LEDSEL is an external pin. Pin# Note: During reset, these pins are inputs for internal testing. Port 2 LED indicators, defined as below: P2LED2 P2LED1 P2LED0 LEDSEL = 0 LINK/ACT FULLD/COL SPEED LEDSEL = 1 100LINK/ACT 10LINK/ACT FULLD
Note: LEDSEL is an external pin. Pin# Note: During reset, these pins are inputs for internal testing and don't pull these pins down. 7 8 9 10 11 12 DGND DVCC NC NC NC ADVFC Gnd Pwr Ipd Ipd Ipu Ipu Digital Ground Digital Vcc NC NC NC 1= advertise the switch's flow control capability via auto-negotiation. 0 = will not advertise the switch's flow control capability via auto-negotiation. 1 = enable Auto-negotiation on port 2. 0 = disable Auto-negotiation on port 2. 1 = Force port 2 in 100BT if P2ANEN = 0. 0 = Force port 2 in 10BT if P2ANEN = 0. 1 = port 2 default to full duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in Full duplex mode if P2ANEN = 0. 0 = port 2 default to half duplex mode if P2ANEN = 1 and auto negotiation fails. Force port 2 in Half duplex mode if P2ANEN = 0. 1 = always enable (force) port 2 flow control feature
13 14 15
P2ANEN P2SPD P2DPX
Ipu Ipd Ipd
16
P2FFC
Ipd
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Pin #
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Name
NC NC NC NC DGND DVCC NC NC NC NC NC NC NC P1ANEN P1SPD P1DPX
Type
Opu Ipd Ipd Opd Gnd Pwr Ipd O O O Ipd Ipd Ipd Ipu Ipd Ipd
Description
0 = flow control feature enable is determined by Auto Negotiation result. NC NC. NC NC Digital Ground Digital Vcc NC NC NC NC NC NC NC 1 = enable Auto-negotiation on port 1 0 = disable Auto-negotiation on port 1 1 = Force port 1 in 100BT if P1ANEN = 0. 0 = Force port 1 in 10BT if P1ANEN = 0. 1 = port 1 default to full duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in Full duplex mode if P1ANEN = 0. 0 = port 1 default to half duplex mode if P1ANEN = 1 and auto negotiation fails. Force port 1 in Half duplex mode if P1ANEN = 0. 1 = always enable (force) port 1 flow control feature 0 = port 1 flow control feature enable is determined by Auto Negotiation result. NC NC Chip power down input 1.8v gnd 1.8v vdd 1.8v gnd Factory test pin Factory test pin 1.8v gnd 1.8v vdd NC Physical receive or transmit signal + differential Physical receive or transmit signal - differential Physical receive or transmit Physical receive or transmit 3.3v vdd 3.3v vdd Physical receive or transmit Physical receive or transmit signal + differential signal - differential
33
P1FFC
Ipd
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
NC NC PWRDN AGND AVDD AGND MUX1 MUX2 AGND AVDD NC RXP1 RXM1 AGND TXP1 TXM1 VDDTX33 VDDRX33 RXP2 RXM2 AGND
Ipd Ipd I GND PWR GND I I GND PWR I I/O I/O GND I/O I/O PWR PWR I/O O/O GND
signal + differential signal - differential
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Pin #
55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
Pin Name
TXP2 TXM2 AVDD AGND TEST1 TEST2 ISET AGND AVDD AGND X1 X2 RST_N BPEN SMAC LEDSEL
Type
I/O I/O PWR GND I I O GND PWR GND I O Ipu Ipd Ipd Ipd
Description
Physical receive or transmit signal + differential Physical receive or transmit signal - differential 1.8v gnd 1.8v vdd Factory test pin Factory test pin Set physical transmit output current 1.8v gnd 1.8v vdd 1.8v vdd 25 Mhz crystal connection 25 Mhz crystal connection Hardware reset pin Half Duplex Backpressure Enable Special Mac Mode. In this mode, the switch will do faster backoffs than normal. To select LED display mode.
PXLED2 PXLED1 PXLED0 LEDSEL = 0 LINK/ACT FULLD/COL SPEED LEDSEL = 1 100LINK/ACT 10LINK/ACT FULLD
71 72 73 74 75 76 77
SMTXEN SMTXD3 SMTXD2 SMTXD1 SMTXD0 SMTXER SMTXC
Ipd Ipd Ipd Ipd Ipd Ipd Ipd/O
Switch MII transmit enable Switch MII transmit data bit 3 Switch MII transmit data bit 2 Switch MII transmit data bit 1 Switch MII transmit data bit 0 Switch MII transmit error Switch MII transmit clock. Output in PHY MII mode Input in MAC MII mode Digital Ground Digital Vcc Switch MII receive clock. Output in PHY MII mode Input in MAC MII mode Switch MII receive data valid Switch MII receive data bit 3 Strap option: PD (default) = Disable Switch MII full-
78 79 80 81 82
DGND DVCC SMRXC SMRXDV SMRXD3
Gnd Pwr Ipd/O O Ipd / O
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Pin #
83 84 85 86 87 88 89
Pin Name
SMRXD2 SMRXD1 SMRXD0 SCOL SCRS SCONF1 SCONF0
Type
Ipd / O Ipd / O Ipd / O Ipd / O Ipd / O Ipd Ipd
Description
duplex flow control; PU = Enable Switch MII fullduplex flow control Switch MII receive bit 2. Strap option: PD (default) = Switch MII in half duplex mode; PU = Switch MII in full-duplex mode. Switch MII receive bit 1. Strap option: PD (default) = Switch MII in 100Mbps mode; PU = Switch MII in 10Mbps mode Switch MII receive bit 0; Strap option: see register 11[1]. Switch MII collision detect Switch MII carrier sense Switch MII interface configuration
(SCONF1, SCONF0) (0,0) (0,1) (1,0) (1,1) Description disable, output tri-stated phy mode MII mac mode MII phy mode SNI
90 91 92 93
DGND DVCC PRSEL1 PRSEL0
Gnd Pwr Ipd Ipd
Digital Ground Digital Vcc Priority Select. Select queue servicing if using split queues. Use the table below to select desired servicing. Note that this selection effects all split transmit queue ports in the same way.
(PRSEL,PRSEL0) (0,0) (0,1) (1,0) (1,1) Description Transmit all high priority before low prioirtu Transmit high priority and low priority at 10:1 ratio. Transmit high priority and low priority at 5:1 ratio. Transmit high priority and low priority at 2:1 ratio.
94 95 96 97 98 99
MDC MDIO SPIQ SCL SDA SPIS_N
Ipu Ipu/O Opu Ipu Ipu/O Ipu
MIIM interface clock input MIIM interface data I/O Data output Clock input Data I/O Chip select
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Pin #
100 101
Pin Name
PS1 PS0
Type
Ipd Ipd
Description
Configuration of interface signal for accessing internal Registers
(PS1,PS0) = (0,0) : I2C EEPROM (master) mode (If EEPOM is not detected, the power up default values in KS8993M internal registers will be used) Interface Signals Type Description SPIQ O Unused. (tri-stated) SCL O I2C clock SDA I/O I2C data I/O SPIS_N Ipu Unused. (PS1,PS0) = (0,1) : I2C slave mode. Note the external master to drive SCL. The default device 101-1111- R/W. Interface Signals Type Description SPIQ O Unused. (tri-stated) SCL I I2C clock SDA I/O I2C data I/O SPIS_N Ipu Unused. (PS1,PS0) = (1,0) : SPI slave mode Interface Signals Type Description SPIQ O SPI Data Out SCL I SPI clock SDA I SPI Data In SPIS_N Ipu SPI chip select
102 103
PV31 PV32
Ipu Ipu
Port 3 port based VLAN mask bits. Used to select which ports may trasmit packets received on port 3.
PV31 = 1, port 1 may transmit packets received on port 3. PV31 = 0, port 1 will not transmit any packets received on port 3. PV32 = 1, port 2 may transmit packets received on port 3. PV32 = 0, port 2 will not transmit any packets received on port 3.
104
PV21
Ipu
Port 2 port based VLAN mask bits. Used to select which ports may trasmit packets received on port 2.
PV21 = 1, port 1 may transmit packets received on port 2. PV21 = 0, port 1 will not transmit any packets received on port 2. PV23 = 1, port 3 may transmit packets received on port 2. PV23 = 0, port 3 will not transmit any packets received on port 2.
105
PV23
Ipu
106 107 108 109
DGND DVCC PV12 PV13
Gnd Pwr Ipu Ipu
Digital Ground Digital Vcc Port 1 port based VLAN mask bits. Used to select which ports may trasmit packets received on port 1.
PV12 = 1, port 2 may transmit packets received on port 1. PV12 = 0, port 2 will not transmit any packets received on port 1. PV13 = 1, port 3 may transmit packets received on port 1. PV13 = 0, port 3 will not transmit any packets received on port 1.
110
P3_1PEN
Ipd
Enable port 3 ingress 802.1p priority classification. The enable is from the receive perspective. If the 802.1p processing is disabled or there is no tag,
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Pin #
111
Pin Name
P2_1PEN
Type
Ipd
Description
priority is determined by the P3_PP pin. Enable port 2 ingress 802.1p priority classification. The enable is from the receive perspective. If the 802.1p processing is disabled or there is no tag, priority is determined by the P2_PP pin. Enable port 1 ingress 802.1p priority classification. The enable is from the receive perspective. If the 802.1p processing is disabled or there is no tag, priority is determined by the P1_PP pin. Selects transmit queue split on port 3. The split sets up high and low priority queues. Note: packet priority classification is done on ingress ports, via port based,802.1p or TOS based scheme. The priority enabled queueing on port 3 is set by P3_TXQ2 Selects transmit queue split on port 2. The split sets up high and low priority queues. Note: packet priority classification is done on ingress ports, via port based,802.1p or TOS based scheme. The priority enabled queueing on port 2 is set by P2_TXQ2 Selects transmit queue split on port 1. The split sets up high and low priority queues. Note: packet priority classification is done on ingress ports, via port based,802.1p or TOS based scheme. The priority enabled queueing on port 1 is set by P2_TXQ2 Port 3 ingress default port priority. Note: 802.1p and Diffserv, if applicable, will take precedence. Port 2 ingress default port priority. Note: 802.1p and Diffserv, if applicable, will take precedence. Port 1 ingress default port priority. Note: 802.1p and Diffserv, if applicable, will take precedence. Enable tag insertion on port 3. All packets transmitted from port 3 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port's default tag. Enable tag insertion on port 2. All packets transmitted from port 2 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port's default tag. Enable tag insertion on port 1. All packets transmitted from port 1 will have 802.1Q tag. Packets received with tag will be sent out intact. Packets received without tag will be tagged with ingress port's default tag. Digital Ground Digital VCC Enable tag removal on port 3. All packets transmitted from port 3 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q
112
P1_1PEN
Ipd
113
P3_TXQ2
Ipd
114
P2_TXQ2
Ipd
115
P1_TXQ2
Ipd
116 117 118 119
P3_PP P2_PP P1_PP P3_TAGINS
Ipd Ipd Ipd Ipd
120
P2_TAGINS
Ipd
121
P1_TAGINS
Ipd
122 123 124
DGND DVCC P3_TAGRM
Gnd Pwr Ipd
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Pin #
125
Pin Name
P2_TAGRM
Type
Ipd
Description
tag. Packets received without tag will be sent out intact. Enable tag removal on port 2. All packets transmitted from port 2 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. Enable tag removal on port 1. All packets transmitted from port 1 will not have 802.1Q tag. Packets received with tag will be modified by removing 802.1Q tag. Packets received without tag will be sent out intact. Scan Test Enable Scan Test Scan Mux Enable
126
P1_TAGRM
Ipd
127 128
TESTEN SCANEN
Ipd Ipd
Note:
Pwr = power supply; Gnd = ground; I = input; O = output; I / O = bi-directional; Ipu = input w/ internal pull-up; Ipd = input w/ internal pull-down; Ipd / O = input w/ internal pull-down during reset, output pin otherwise; Ipu / O = input w/ internal pull-up during reset, output pin otherwise; PU = strap pin pull-up; PD = strap pull-down; Otri = output tristated; Opu = Output with internal pull-up Opd = Output with internal pull-down
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
2.0 Advanced Functions
2.1 Port Mirroring Support
KS8993M supports "port mirror" comprehensively as: (1), "receive only" mirror on a port. All the packets received on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be "rx sniff", and port 2 is programmed to be the "sniffer port". A packet, received on port 1, is destined to port 2 after the internal look up. The KS8993M will forward the packet to both port 2 and port 3. KS8993M can optionally forward even "bad" received packets to port 3. (2), "transmit only" mirror on a port. All the packets transmitted on the port will be mirrored on the sniffer port. For example, port 1 is programmed to be "tx sniff", and port 3 is programmed to be the "sniffer port". A packet, received on any of the ports, is destined to port 1 after the internal look up. The KS8993M will forward the packet to both port 1 and port 3. (3), "receive and transmit" mirror on two ports. All the packets received on port A AND transmitted on port B will be mirrored on the sniffer port. To turn on the "AND" feature, set register 5 bit 0 to 1. For example, port 1 is programmed to be "rx sniff", port 2 is programmed to be "transmit sniff" and port 3 is programmed to be the "sniffer port". A packet, received on port 1, is destined to port 2 after the internal look up. The KS8993M will forward the packet to port 2 only, since it does not meet the "AND" condition. A packet, received on port 1, is destined to port 2 after the internal look up. The KS8993M will forward the packet to both port 2 and port 3. Multiple ports can be selected to be "rx sniffed" or "tx sniffed". And any port can be selected to be the "sniffer port". All these per port features can be selected through register 17.
2.2 VLAN support
KS8993M supports 16 active VLANs out of 4096 possible VLANs specified in IEEE 802.1Q. KS8993M provides a 16-entry VLAN table, which converts VID (12 bits) to FID (4bits) for address look up. If a non-tagged or null-VID-tagged packet is received, the ingress port VID is used for look up. In the VLAN mode, the look up process starts with VLAN table look up to determine whether the VID is valid. If the VID is not valid, the packet will be dropped and its address will not be learned. If the VID is valid, FID is retrieved for further look up. FID+DA is used to determine the destination port. FID+SA is used for learning purposes. Micrel - Kendin Confidential Information 9 Rev. 1.00 7/12/02
KS8993M (3 Port 10/100 Integrated Switch with PHY)
FID+DA look up in the VLAN mode DA found in USE FID Static MAC flag? table No Don't care FID match? DA+FID found in dynamic MAC table Don't care No Action
No
Don't care
Don't care
Yes
Yes
0
Don't care
Don't care
Yes
1
No
No
Yes
1
No
Yes
Yes
1
Yes
Don't care
Broadcast to the membership ports defined in the VLAN table bit [20:16] Send to the destination port defined in the dynamic MAC table bit[54:52] Send to the destination port(s) defined in the static MAC table bit[52:48] Broadcast to the membership ports defined in the VLAN table bit [20:16] Send to the destination port defined in the dynamic MAC table bit[54:52] Send to the destination port(s) defined in the static MAC table bit[52:48]
FID+SA look up in the VLAN mode SA+FID found in dynamic MAC table No Yes Action
The SA+FID will be learned into the dynamic table. Time stamp will be updated.
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Advanced VLAN features are also supported in KS8993M, such as "VLAN ingress filtering" and "discard non PVID" defined in register 18 bit 6 and bit 5. These features can be controlled on a port basis.
2.3 QoS Priority support
This feature provides QOS for applications such as VOIP, video conferencing, and mission critical applications. The KS8993M per port transmit queue could be split into two priority queues, high priority and low priority queues. The splitting feature could be optionally per port enabled (using pin Px_TXQ2). If a port is split, high priority packets will be put in the high priority queue. If a port's transmit queue is not split, high priority and low priority packets will be treated equally. There are four priority schemes (selected by pins PRSEL1 and PRSEL0): (1), transmit high priority packets always before low priority packets, i.e. A low priority packet could be transmitted only when the high priority queue is empty. (2), 10/1 ratio, transmit a low priority after every 10 high priority packets transmitted if both queues are busy. (3), 5/1 ratio, (4) 2/1 ratio. Incoming packet priority could be classified in two ways, port-based or 802.1p. Port based priority: Each port could be individually specified as a high priority receiving port (using pin Px_PP). All the packets received at the high priority receiving port will be marked high priority and sent to the high priority transmit queue if the corresponding queue is split. 802.1p based priority: 802.1p based priority could be enabled by pins Px_1PEN. KS8993M will examine incoming packets to determine whether they are tagged and retrieve the corresponding priority information. The priority field in the VLAN tag is 3 bits wide and is compared against "priority base value specified by register 2 bit 6-4. (the default value is 0x4). If a received packet has an equal or larger priority value than the "priority base" value, the packet will be put in the high priority transmit queue if the corresponding queue is split. KS8993M can optionally remove or insert priority tagged frame's header (2 bytes of tag protocol identifier 0x8100 and 2 bytes of tag control information). If a transmitting port has its corresponding Px_TAGINS set (meaning tag insertion), the transmitting logic will automatically insert tag with source port's default tag value. For already tagged packets, KS8993M will pass the original packet without changing its tag content. If a transmitting port has its corresponding Px_TAGRM set (meaning tag removal), the transmitting logic will automatically remove "802.1Q tag". For untagged packets, KS8993M will pass the original packet without changing any content. Either tag insertion or removal will cause CRC recalculation.
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
2.4 Rate Limit Support
KS8993M supports hardware rate limiting on "receive" and "transmit" independently on a per port basis. It also supports rate limiting in a priority or non-priority environment. The rate limit starts from 0 kbps and goes up to the line rate in steps of 32 kbps. The KS8993M uses one second as an interval. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the number of bytes during this interval. For receive, if the number of bytes exceeds the programmed limit, the switch will stop receiving packets on the port until the "one second" interval expires. There is an option provided for flow control to prevent packet loss. If the rate limit is programmed greater than or equal to 128kbps and the byte counter is 8Kbytes below the limit, the flow control will be triggered. If the rate limit is programmed lower than 128kbps and the byte counter is 2Kbytes below the limit, the flow control will be triggered. For transmit, if the number of bytes exceeds the programmed limit, the switch will stop transmitting packets on the port until the "one second" interval expires. If priority is enabled, the KS8993M can support different rate controls for both high priority and low priority packets. This can be programmed through registers.
2.5 Static MAC address table
KS8993M has a static and a dynamic address table. When a DA look up is requested, both tables will be searched to make a packet forwarding decision. When an SA look up is requested, only the dynamic table is searched for aging, migration and learning purposes. The static DA look up result will have precedence over the dynamic DA look up result. If there are DA matches in both tables, the result from the static table will be used. The static table can only be accessed and controlled by an external SPI master (usually a processor). The entries in the static table will not be aged out by KS8993M. An external device does all addition, modification and deletion. Note: Register bit assignments are different for static MAC table reads and static MAC table write as shown in the two tables below.
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Format of static MAC table (8 entries)
Bit 57-54 53 52 51 50-48 Name FID Use FID override valid Forwarding ports R/W W W W W W Description Filter VLAN ID, representing one of the 16 active VLANs. =1, use (FID+MAC) to look up in static table =0, use MAC only to look up in static table =1, override port setting "transmit enable=0" or "receive enable=0" setting. =0, no override =1, this entry is valid, the look up result will be used =0, this entry is not valid The 3 bits control the forward ports, ex 001, forward to port 1 010, forward to port 2 100, forward to port 3 110, forward to port 2 and port 3 111, broadcasting (excluding the ingress port) 48 bit MAC address Default 0000 0 0 0 00000
47-0
MAC address
W
0x0
2.6 VLAN table
VLAN table is used to do VLAN table look up. If 802.1Q VLAN mode is enabled (Register 5 bit 7 =1), this table will be used to retrieve VLAN information that the ingress packet is associated with. The information includes FID(fiter ID), VID(VLAN ID), VLAN membership described below: Format of static VLAN table (16 entries) Bit Name R/W Description 19 Valid R/W =1, the entry is valid =0, entry is invalid 18-16 Membership R/W Specify which ports are members of the VLAN. If a DA look up fails (no match in both static and dynamic tables), the packet associated with this VLAN will be forwarded to ports specified in this field. Eg. 11001 means port 5,4, and 1 are in this VLAN. 15-12 FID R/W Filter ID. KS8993M supports 16 active VLANs represented by these four bit fields. FID is the mapped ID. If 802.1Q VLAN is enabled, the look up will be based on FID+DA and FID+SA. 11-0 VID R/W IEEE 802.1Q 12 bit VLAN ID
Default 1 111
0
1
If 802.1Q VLAN mode is enabled, KS8993M will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up. If the VID is not valid, the packet will be dropped and no address learning will take place. If the VID is valid, the FID is retrieved. The
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
FID+DA and FID+SA lookups are performed. The FID+DA look up determines the forwarding ports. If FID+DA fails, the packet will be broadcasted to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA will be learned.
2.7 Dynamic MAC address table
This table is read only. The contents are maintained by KS8993M only.
Format of dynamic MAC address table (1K entries)
Bit 71 Name Data not ready MAC empty No of valid entries R/W RO Description =1, The entry is not ready, retry until this bit is set to 0. =0, The entry is ready =1, there is no valid entry in the table =0, there are valid entries in the table Indicates how many valid entries in the table 0x3ff means 1 K entries 0x1 means 2 entries 0x0 and bit 67 = 0: means 1 entry 0x0 and bit 67 = 1: means 0 entry 2-bit counters for internal aging The source port where FID+MAC is learned. 00 port 1 01 port 2 10 port 3 Filter ID Default
66 65-56
RO RO
1 0
55-54 53-52
Time stamp Source port
RO RO
0x0
51-48
FID
RO
0x0
2.8 MIB (Management Information Base) counters
The MIB counters are provided on per port basis. The indirect memory is as below: For port 1
Port 1 MIB Counter Indirect Memory Offsets
Offset 0x0 0x1 0x2 0x3 0x4 Counter Name RxLoPriorityByte RxHiPriorityByte RxUndersizePkt RxFragments RxOversize Description Rx lo-priority (default) octet count including bad pkts Rx hi-priority octet count including bad pkts Rx undersize pkts w/ good CRC Rx fragment pkts w/ bad CRC, symbol errors or alignment errors Rx oversize pkts w/ good CRC (max: 1536 or 1522 bytes)
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
0x5 RxJabbers Rx pkts longer than 1522B w/ either CRC errors, Alignment errors, or symbol errors. (Depends on max packet size setting). Rx pkts w/ invalid data symbol and legal packet size. Rx pkts within (64,1522) bytes w/ an integral number of bytes and a bad CRC (Upper limit depends on max packet size setting). Rx pkts within (64,1522) bytes w/ a non-integral number of bytes and a bad CRC (Upper limit depends on max packet size setting). The number of MAC control frames received by a port with 88-08h in EtherType field. The number of PAUSE frames received by a port. PAUSE frame is qualified with EtherType (88-08h), DA, control opcode (00-01), data length (64B min), and a valid CRC Rx good broadcast pkts (not including errored broadcast pkts or valid multicast pkts) Rx good multicat pkts (not including MAC control frames, errored multicast pkts or valid broadcast pkts) Rx good unicast packets Total Rx pkts (bad pkts included) that were 64 octets in length Total Rx pkts (bad pkts included) that are between 65 and 127 octets in length Total Rx pkts (bad pkts included) that are between 128 and 255 octets in length Total Rx pkts (bad pkts included) that are between 256 and 511 octets in length Total Rx pkts (bad pkts included) that are between 512 and 1023 octets in length Total Rx pkts (bad pkts included) that are between 1024 and 1522 octets in length (Upper limit depends on max packet size setting). Tx lo-priority good octet count, including PAUSE pkts Tx hi-priority good octet count, including PAUSE pkts The number of times a collision is detected later than 512 bit-times into the Tx of a pkt
0x6 0x7 0x8
RxSymbolError RxCRCerror RxAlignmentError
0x9 0xA
RxControl8808Pkts RxPausePkts
0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13
RxBroadcast RxMulticast RxUnicast Rx64Octets Rx65to127Octets Rx128to255Octets Rx256to511Octets Rx512to1023Octets Rx1024to1522Octets
0x14 0x15 0x16
TxLoPriorityByte TxHiPriorityByte TxLateCollision
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F
TxPausePkts TxBroadcastPkts TxMulticastPkts TxUnicastPkts TxDeferred TxTotalCollision TxExcessiveCollision TxSingleCollision TxMultipleCollision
The number of PAUSE frames transmitted by a port Tx good broadcast pkts (not including errored broadcast or valid multicast pkts) Tx good multicast pkts (not including errored multicast pkts or valid broadcast pkts) Tx good unicast pkts Tx pkts by a port for which the 1st Tx attempt is delayed due to the busy medium Tx total collision, half duplex only A count of frames for which Tx fails due to excessive collisions Successfully Tx frames on a port for which Tx is inhibited by exactly one collision Successfully Tx frames on a port for which Tx is inhibited by more than one collision
For port 2, the base is 0x20, same offset definition (0x20-0x3f) For port 3, the base is 0x40, same offset definition (0x40-0x5f)
Format of Per Port MIB Counters (16 entries)
Bit 31 30 29-0 Name Overflow Count Valid Counter values R/W RO RO RO Description =1, Counter overflow =0, No Counter overflow =1, Counter value is valid =0, Counter value is not valid Counter value Default 0 0 0
Table 2-All Port Dropped Packet MIB Counters
Offset 0x100 0x101 0x102 0x103 0x104 0x105 Counter Name Port1 TX Drop Packets Port2 TX Drop Packets Port3 TX Drop Packets Port1 RX Drop Packets Port2 RX Drop Packets Port3 RX Drop Packets Description Tx packets dropped due to lack of resources Tx packets dropped due to lack of resources Tx packets dropped due to lack of resources Rx packets dropped due to lack of resources Rx packets dropped due to lack of resources Rx packets dropped due to lack of resources
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Format of All Port Dropped Packet MIB Counters
Bit 30-16 15-0 Name R/W Description Default Reserved N/A Reserved N/A Counter RO Counter value 0 values Note: All port dropped packet MIB counters do not indicate overflow or validity; therefore the application must keep track of overflow and valid conditions.
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
3.0 Package Outline and Dimensions
128 P in P Q F P P ackage O utline D raw ing
17.2 +/- 0.2 m m 14.0 +/- 0.1 m m 12.5 m m
1
23.2 +/- 0.2 m m
20.0 +/- 0.1 m m
18.5 m m
0.5 m m
3.4 m m m ax.
Figure - Package Outline Thermal resistance JA = 32 C/W
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KS8993M (3 Port 10/100 Integrated Switch with PHY)
Micrel Inc. - Kendin Operations 486 Mercury Drive Sunnyvale, CA 94085 (c) Micrel, Inc. 2001 All rights reserved Micrel, Kendin are registered trademarks of Micrel and its subsidiaries in the United States and certain other countries. All other trademarks are the property of their respective owners.
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